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INTEGRATED CIRCUITS
DATA SHEET
TZA3019 2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
Preliminary specification File under Integrated Circuits, IC19 2000 Apr 10
Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
FEATURES * Dual postamplifier * Single 3.3 V power supply * Wideband operation from 50 kHz to 2.5 GHz (typical value) * Fully differential * Channels are delay matched * On-chip DC-offset compensations without external capacitor * Interfacing with positive or negative supplied logic * Switching possibility between channels * Positive Emitter Coupled Logic (PECL) or Current-Mode Logic (CML) compatible data outputs adjustable from 200 to 800 mV (p-p) single-ended * Power-down capability for unused outputs and detectors * Rise and fall times 80 ps (typical value) * Possibility to invert the output of each channel separately * Input level-detection circuits for Received Signal Strength Indicator (RSSI) or Loss Of Signal (LOS) detection, programmable from 0.4 to 400 mV (p-p) single-ended, with open-drain comparator output for direct interfacing with positive or negative logic * Reference voltage for output level and LOS adjustment * Automatic strongest input signal switch possibility (TZA3019 version B) * HTQFP32 or HBCC32 plastic package with exposed pad. APPLICATIONS
TZA3019
* Postamplifier for Synchronous Digital Hierarchy and Synchronous Optical Network (SDH/SONET) transponder * SDH/SONET wavelength converter * Crosspoint or channel switch * PECL driver * Fibre channel arbitrated loop * Protection ring * Monitoring * Signal level detectors * Swing converter CML 200 mV (p-p) to PECL 800 mV (p-p) * Port bypass circuit * 2.5 GHz clock amplification. GENERAL DESCRIPTION The TZA3019 is a low gain postamplifier multiplexer with a dual RSSI and/or LOS detector that is designed for use in critical signal path control applications, such as loop-through, redundant channel switching or Wavelength Division Multiplexing (WDM). The signal path is unregistered, so no clock is required for the data inputs. The signal path is fully differential and delay matched. It is capable of operating from 50 kHz to 2.5 GHz. The TZA3019 HTQFP32 and HBCC32 packages can be delivered in three versions: * TZA3019AHT and TZA3019AV with two RSSI signals * TZA3019BHT and TZA3019BV with one RSSI and one LOS signal * TZA3019CHT and TZA3019CV with two LOS signals.
ORDERING INFORMATION TYPE NUMBER TZA3019AHT TZA3019BHT TZA3019CHT TZA3019AV TZA3019BV TZA3019CV TZA3019U PACKAGE NAME HTQFP32 HTQFP32 HTQFP32 HBCC32 HBCC32 HBCC32 - DESCRIPTION plastic, heatsink thin quad flat package; 32 leads; body 5 x 5 x 1 mm plastic, heatsink thin quad flat package; 32 leads; body 5 x 5 x 1 mm plastic, heatsink thin quad flat package; 32 leads; body 5 x 5 x 1 mm plastic, heatsink bottom chip carrier; 32 terminals; body 5 x 5 x 0.65 mm plastic, heatsink bottom chip carrier; 32 terminals; body 5 x 5 x 0.65 mm plastic, heatsink bottom chip carrier; 32 terminals; body 5 x 5 x 0.65 mm bare die; 2.22 x 2.22 x 0.28 mm VERSION SOT547-2 SOT547-2 SOT547-2 SOT560-1 SOT560-1 SOT560-1 -
2000 Apr 10
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Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
BLOCK DIAGRAM
TZA3019
handbook, full pagewidth
VEE1A LOSTH1
32 10
25
VEE1B
LOS DETECTOR
1x offset
27
RSSI1
LEVEL1 INV1 S1 GND1A IN1 IN1Q GND1A
12 29 31 1 2 3 4
TZA3019AHT TZA3019AV
level
24 SWITCH 23 22 A1A A1B 21
GND1B OUT1 OUT1Q GND1B
TEST
15
DFT
BAND GAP REFERENCE
14
Vref
GND2A IN2Q IN2 GND2A S2 INV2 LEVEL2
8 7 6 5 30 28 13 level SWITCH A2A A2B
17 18 19 20
GND2B OUT2Q OUT2 GND2B
offset LOS DETECTOR 11 9 1x
26
RSSI2
LOSTH2 VEE2A
16
VEE2B
MGT028
Fig.1 Block diagram (TZA3019AHT and TZA3019AV).
2000 Apr 10
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Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
TZA3019
handbook, full pagewidth
VEE1A LOSTH1
32 10
25
VEE1B
LOS DETECTOR offset 12 29 31 1 2 3 4 A1A A1B
5 k
27
LOS1
TZA3019BHT TZA3019BV
level
LEVEL1 INV1 S1 GND1A IN1 IN1Q GND1A
24 SWITCH 23 22 21
GND1B OUT1 OUT1Q GND1B
TEST
15
DFT
BAND GAP REFERENCE
14
Vref
GND2A IN2Q IN2 GND2A S2 INV2 LEVEL2
8 7 6 5 30 28 13 level SWITCH A2A A2B
17 18 19 20
GND2B OUT2Q OUT2 GND2B
offset LOS DETECTOR 11 9 1x
26
RSSI2
LOSTH2 VEE2A
16
VEE2B
MGT027
Fig.2 Block diagram (TZA3019BHT and TZA3019AV).
2000 Apr 10
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Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
TZA3019
handbook, full pagewidth
VEE1A LOSTH1
32 10
25
VEE1B
LOS DETECTOR offset 12 29 31 1 2 3 4 A1A A1B
5 k
27
LOS1
TZA3019CHT TZA3019CV
level
LEVEL1 INV1 S1 GND1A IN1 IN1Q GND1A
24 SWITCH 23 22 21
GND1B OUT1 OUT1Q GND1B
TEST
15
DFT
BAND GAP REFERENCE
14
Vref
GND2A IN2Q IN2 GND2A S2 INV2 LEVEL2
8 7 6 5 30 28 13 level SWITCH A2A A2B
17 18 19 20
GND2B OUT2Q OUT2 GND2B
LOS DETECTOR
offset
5 k
26
LOS2
LOSTH2 VEE2A
11 9 16
VEE2B
MGS553
Fig.3 Block diagram (TZA3019CHT and TZA3019CV).
2000 Apr 10
5
Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
PINNING PIN SYMBOL TZA3019xHT/xV(1) A GND1A IN1 IN1Q GND1A n.c n.c GND2A IN2 IN2Q GND2A VEE2A LOSTH1 1 2 3 4 - - 5 6 7 8 9 10 B 1 2 3 4 - - 5 6 7 8 9 10 C 1 2 3 4 - - 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 11 12 S I I S - - S I I S S I ground for input 1 and LOS1 circuits PAD TYPE(2) DESCRIPTION
TZA3019
differential circuit 1 input; complimentary to pin IN1Q; DC bias level is set internally at approximately -0.33 V differential circuit 1 input; complimentary to pin IN1; DC bias level is set internally at approximately -0.33 V ground for input 1 and LOS1 circuits not connected not connected ground for input 2 and LOS2 circuits differential circuit 2 input; complimentary to pin IN2Q; DC bias level is set internally at approximately -0.33 V differential circuit 2 input; complimentary to pin IN2; DC bias level is set internally at approximately -0.33 V ground for input 2 and LOS2 circuits negative supply voltage for input 2 and LOS2 circuits Input for level detector programming of input 1 circuit; threshold level is set by connecting external resistors between pins GND1A and Vref. When forced to VEE2A or not connected, the LOS1 circuit will be switched off. Input for level detector programming of input 2 circuit; threshold level is set by connecting external resistors between pins GND2A and Vref. When forced to VEE2A or not connected, the LOS2 circuit will be switched off. not connected Input for programming output level of output 1 circuit; output level is set by connecting external resistors between pins GND1A and Vref. When forced to GND1A or not connected, pins OUT1 and OUT1Q will be switched off. Input for programming output level of output 2 circuit; output level is set by connecting external resistors between pins GND2A and Vref. When forced to GND2A or not connected, pins OUT2 and OUT2Q will be switched off. reference voltage for level circuit and LOS threshold programming; typical value is -1.6 V; no external capacitor allowed for test purposes only; to be left open-circuit in the application negative supply voltage for output 2 circuit ground for output 2 circuit PECL or CML compatible differential circuit 2 output; complimentary to pin OUT2
LOSTH2
11
11
11
13
I
n.c LEVEL1
- 12
- 12
- 12
14 15
- I
LEVEL2
13
13
13
16
I
Vref n.c TEST VEE2B GND2B OUT2Q
14 - 15 16 17 18
14 - 15 16 17 18
14 - 15 16 17 18
17 18 19 20 21 22
O - I S S O
2000 Apr 10
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Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
PIN SYMBOL TZA3019xHT/xV(1) A OUT2 GND2B n.c n.c GND1B OUT1Q OUT1 GND1B VEE1B RSSI2 LOS2 RSSI1 LOS1 INV2 INV1 S2 S1 VEE1A VEEP Notes 1. The `x' in TZA3019xHT/xV represents versions A, B and C. 19 20 - - 21 22 23 24 25 26 - 27 - 28 29 30 31 32 pad B 19 20 - - 21 22 23 24 25 26 - - 27 28 29 30 31 32 pad C 19 20 - - 21 22 23 24 25 - 26 - 27 28 29 30 31 32 pad 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 - O S - - S O O S S O PAD TYPE(2) DESCRIPTION
TZA3019
PECL or CML compatible differential circuit 2 output; complimentary to pin OUT2Q ground for output 2 circuit not connected not connected ground for output 1 circuit PECL or CML compatible differential circuit 1 output; complimentary to pin OUT1 PECL or CML compatible differential circuit 1 output; complimentary to pin OUT1Q ground for output 1 circuit negative supply voltage for output 1 circuit output of received signal strength indicator of detector
O-DRN output loss of signal detector 2; detection of input 2 signal; direct drive of positive or negative supplied logic via internal 5 k resistor O output of received signal strength indicator of detector O-DRN output loss of signal detector 2; detection of input 2 signal; direct drive of positive or negative supplied logic via internal 5 k resistor TTL TTL TTL TTL S S input to invert the signal of pins OUT2 and OUT2Q; directly positive (inverted) or negative supplied logic driven input to invert the signal of pins OUT1 and OUT1Q; directly of positive (inverted) or negative supplied logic driven input selector output 2 circuit; directly positive (inverted) or negative supplied logic driven input selector output 1 circuit; directly positive (inverted) or negative supplied logic driven negative supply voltage for input 1 and LOS1 circuits negative supply voltage pad (exposed die pad)
2. Pin type abbreviations: O = output, I = input, S = power supply, TTL = logic input and O-DRN = open-drain output.
2000 Apr 10
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Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
TZA3019
handbook, full pagewidth
26 RSSI2/LOS2
27 RSSI1/LOS1
32 VEE1A
GND1A IN1 IN1Q GND1A GND2A IN2 IN2Q GND2A
1 2 3 4 exposed pad
25 VEE1B
29 INV1
28 INV2
31 S1
30 S2
24 GND1B 23 OUT1 22 OUT1Q 21 GND1B
TZA3019xHT
5 6 7 8 VEEP 20 GND2B 19 OUT2 18 OUT2Q 17 GND2B
LOSTH2 11
LOSTH1 10
LEVEL1 12
LEVEL2 13
Vref 14
TEST 15
VEE2B 16
VEE2A 9
MGS554
Fig.4 Pin configuration HTQFP32.
RSSI1/LOS1
handbook, full pagewidth
RSSI2/LOS2 26
VEE1A
INV1
GND1A IN1 IN1Q GND1A GND2A IN2 IN2Q GND2A
1 2 3 4 5 6 7 8 9 VEE2A
32
31
30
29
28
INV2
27
25 24 23 22 GND1B OUT1 OUT1Q GND1B GND2B OUT2 OUT2Q GND2B
exposed pad
TZA3019xV
21 20 19 VEEP 18 17
10 LOSTH1
11 LOSTH2
12 LEVEL1
13 LEVEL2
14 Vref
15 TEST
16 VEE2B
VEE1B
MGT029
S1
Fig.5 Pin configuration HBCC32.
2000 Apr 10
S2
8
Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
FUNCTIONAL DESCRIPTION The TZA3019 is a dual postamplifier with multiplexer and loss of signal detection see Figs 1, 2 and 3. The RF path starts with the multiplexer, which connects an amplifier to one of the two inputs. It is possible to invert the output for easy layout of the Printed-Circuit Board (PCB). The signal is amplified to a certain level. To guarantee this level with minimum distortion over the temperature range and level range, an active control part is added. The offset compensation circuit following the inverter minimizes the offset. The Received Signal Strength Indicator (RSSI) or the Loss Of Signal (LOS) detection uses a 7-stage `successive detection' circuit. It provides a logarithmic output. The LOS is followed by a comparator with a programmable threshold. The input signal level-detection is implemented to check if the input signal voltage is above the user programmed level. This can insure that data will only be transmitted when the input signal-to-noise ratio is sufficient for low bit error rate system operation. A second offset compensation circuit minimizes the offset of the logarithmic amplifier. RF input circuit The input circuit contains internal 50 resistors decoupled to ground via an internal common mode 12 pF capacitor (see Fig.6). The input pins are DC-biased at approximately -0.33 V by an internal reference generator. The TZA3019 can be DC-coupled, but AC-coupling is preferred. In case of DC-coupling, the driving source must operate within the allowable input range (-1.0 to +0.3 V). A DC-offset voltage of more than a few millivolts should be avoided, since the internal DC-offset compensation circuit has a limited correction range. When AC-coupling is used, if no DC-compatibility is required, the values of the coupling capacitors must be large enough to pass the lowest input frequency of interest. Capacitor tolerance and resistor variation must be included for an accurate calculation. Do not use signal frequencies around the low cut-off circuit frequencies (f-3dB(l) = 50 kHz for the postamplifiers and f-3dB(l) = 1 MHz for the LOS circuits). RF output circuit Matching the main amplifier outputs (see Fig.7) is not mandatory. In most applications, the transmission line receiving end will be properly matched, while very little reflections occur. Matching the transmitting end to absorb reflections is only recommended for very sensitive applications. 2000 Apr 10 9 Postamplifier level adjustment
TZA3019
In such cases, pull-up resistors of 100 should be connected as close as possible to the IC from pins OUT1 and OUT1Q, and pins OUT2 and OUT2Q to VEE1B and VEE2B respectively. These matching resistors are not needed in most applications.
handbook, halfpage
GND1A, GND2A 12 pF 420
50 IN1, IN2 IN1Q, IN2Q
50
MGS555
VEE1A, VEE2A
Fig.6 RF input circuit.
The postamplifier boosts the signal up to PECL levels. The output can be either CML- or PECL-level compatible, adjusted by means of the voltage on pins LEVEL1 and LEVEL2. The DC voltages of pins OUT1 and OUT1Q, and pins OUT2 and OUT2Q match with the DC-levels on pins LEVEL1 and LEVEL2, respectively. Due to the receiving end 50 load resistance, it means that at the same level of Vo(p-p), VLEVEL1 and VLEVEL2 with AC-coupling are not equal to VLEVEL1 and VLEVEL2 with DC-coupling (see Figs 7 and 8). The postamplifier is in power-down state when pin LEVEL1 or LEVEL2 is connected to ground or not connected (see Fig.8). Postamplifier DC offset cancellation loop Offset control loops connected between the inputs of the buffers A1A and A2A and the outputs of the amplifiers A1B and A2B (see Figs 1, 2 and 3) will keep the input of both buffers at their toggle point during the absence of an input signal. The active offset compensation circuit is integrated, so no external capacitor is required. The loop time constant determines the lower cut-off frequency of the amplifier chain. The cut-off frequency of the offset compensations is fixed internally at approximately 5 kHz.
Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
TZA3019
handbook, full pagewidth
GND1A, GND2A R1 100 100
GND1B, GND2B OUT1, OUT2 OUT1Q, OUT2Q 50 50
Vo
LEVEL1, LEVEL2
Vlevel
R2 Vref
REG
0 Vlevel Vo (V) Vo(se)(p-p)
MGS556
Vlevel = 0.5 x Vo(se)(p-p). R1 V level = V ref x --------------------- . R1 + R2 Level detector in power-down mode: VLEVEL1 or VLEVEL2 = VGND.
a. DC-coupling.
handbook, full pagewidth
GND1A, GND2A 100 R1 100
GND1B, GND2B OUT1, OUT2 OUT1Q, OUT2Q 50 50
Vo
LEVEL1, LEVEL2
Vlevel 0
R2 Vref
REG
Vlevel Vo (V)
Vlevel = 1.5 x Vo(se)(p-p). R1 V level = V ref x --------------------- . R1 + R2 Level detector in power-down mode: VLEVEL1 or VLEVEL2 = VGND.
Vo(se)(p-p)
MGL811
b. AC-coupling. Fig.7 RF output configurations.
2000 Apr 10
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Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
TZA3019
handbook, full pagewidth
MGS557
1000 Vo(se)(p-p) (mV) 800 DC-coupled 600 AC-coupled
400
200
0
0
20
40
60
100 80 Vlevel (% of Vref)
Fig.8 Output signal as a function of Vlevel.
TTL logic input of selector and inverter The logic levels are differently defined for positive or negative logic (see Fig.9). It should be noted that positive logic levels are inverted if a negative supply voltage is used. Outputs as a function of switch input pins S1, S2, INV1 and INV2 See Tables 1, 2, 3 and 4. The default values for the switch input pins S1, S2, INV1 and INV2 if not connected, is zero. Table 1 S1 0 1 OUT1 and OUT1Q as function of input S1
Table 2 S2 0 1 Table 3 INV1 0 1 Table 4 INV2
OUT2 and OUT2Q as function of input S2 OUT2 IN2 IN1 OUT2Q IN2Q IN1Q
OUT1 and OUT1Q as function of INV1 OUT1 IN1 or IN2 IN1Q or IN2Q OUT1Q IN1Q or IN2Q IN1 or IN2
OUT2 and OUT2Q as function of INV2 OUT2 IN1 or IN2 IN1Q or IN2Q OUT2Q IN1Q or IN2Q IN1 or IN2
OUT1 IN1 IN2
OUT1Q IN1Q IN2Q
0 1
2000 Apr 10
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Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
TZA3019
handbook, full pagewidth
logic level 1
MGS558
2.0 V
2.0 V
(1)
T TL
0.8 V 0 1.4 V VEE -4 -3 -2 -1 GND 0 +1 +2 VI (V) +3 1.4 V 0.8 V
a. Negative circuit supply voltage VEE and negative logic supply voltage VEE.
handbook, full pagewidth
logic level 1
MGS559
2.0 V
2.0 V
(1)
T TL
0.8 V 0 1.4 V VEE -4 -3 -2 -1 GND 0 +1 +2 VI (V) +3 1.4 V VCC 0.8 V
b. Negative circuit supply voltage VEE and positive logic supply voltage VCC.
handbook, full pagewidth
logic level 1
MGS560
2.0 V
2.0 V
(1)
T TL
0.8 V 0 1.4 V GND -1 0 +1 +2 VCC +3 +4 +5 VI (V) +6 1.4 V 0.8 V
c. Positive circuit supply voltage VCC and positive logic supply voltage VCC.
(1) Level not defined.
Fig.9 Logic levels on pins S1, S2, INV1 and INV2 as a function of the input voltages.
2000 Apr 10
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Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
RSSI and LOS detection The TZA3019 allows AC-signal level detection. This can prevent the outputs from reacting to noise during the absence of a valid input signal, and can insure that data only will be transmitted when the signal-to-noise ratio of the input signal is sufficient to insure low bit error rate system operation. The RSSI detection circuit uses seven limiting amplifiers in a `successive detection' topology to closely approximate logarithmic response over a total range of 70 dB. The detectors provide full-wave rectification of the AC signals presented at each previous amplifier stage. Their outputs are current drivers. Each cell incorporates a low-pass filter, being the first step in recovering the average value of the demodulated signal of the input frequency. The summed detector output currents are converted to a voltage by an internal load resistor. This voltage is buffered and available in the A and B versions of the TZA3019. When VRSSI is used VLOSTH must be connected to GND to prevent the LOS comparator from switching to the standby mode. The LOS comparator detects an input signal above a fixed threshold, resulting in a LOW-level at the LOS circuit output.The threshold level is determined by the voltage on pins LOSTH1 or LOSTH2 (see Fig.10). A filter with a time constant of 1 s nominal is included to prevent noise spikes from triggering the level detector. The comparator (with internal 3 dB hysteresis) drives an open-drain circuit with an internal resistor (5 k) for direct interfacing to positive or negative logic (see Fig.11). Only available in the B and C versions of the TZA3019. The response is independent of the sign of the input signal because of the particular way the circuit has been built. This is part of the demodulating nature of the detector, which results in an alternating input voltage being transformed to a rectified and filtered quasi DC-output signal. For the TZA3019 the logarithmic voltage slope is = 1/13 dB/mV and is essentially temperature and supply independent through four feedback loops in the reference circuit. The internal LOS detector output voltage is based on Vref. The demodulator characteristic depends on the waveform and the response depends roughly on the input signal RMS value. This influences high frequencies, a square wave input of 2.4 GHz (LOS circuit bandwidth of 2.4 GHz) offsets the intercept voltage by 20%. VLOSTH can be calculated using the following formulae: V LOSTH = V RSSI = S x 20log where S = sensitivity. Example: a 200 mV (p-p) single-ended 1.2 GB/s PRBS signal has an RSSI from 1003 mV. 2000 Apr 10 13
( Vi 18V )
TZA3019
handbook, halfpage3 10
MGS564
Vi(se)(p-p) (mV) 102 LOS1, LOS2 LOW-level
(1) (2)
10 LOS1, LOS2 HIGH-level 1
(3)
10-1 10
20
40 50 60 30 70 VLOSTH1, VLOSTH2 (% of Vref)
-0.16
-0.32
-0.48
-0.64 -0.8 -0.96 -1.12 VRSSI1, VRSSI2 (V)
(1) PRBS pattern input signal with a frequency <1 GHz. (2) Linearity error typically 0.5 dB. (3) = 1/12.5 dB/mV.
Fig.10 Loss of signal assert level.
A full understanding of the offset control loop is useful. The primary purpose of the loop is to extend the lower end of the dynamic range in any case where the offset voltage of the first stage might be high enough to cause later stages to prematurely enter limiting, caused by the high DC-gain of the amplifier system. The offset is automatically and continuously compensated via a feedback path from the last stage. An offset at the output of the logarithmic converter is equivalent to a change of amplitude at the input. Consequently, with DC-coupling, signal absence, either LOW-level or HIGH-level is detected as a full signal, only signals with an average value equal to zero give zero output. Version B can be used for an auto function, which switches the strongest input signal to output 1 and the weakest to output 2. To achieve this output VRSSI2 must be used as the reference voltage for input VLOSTH. Then the output LOS1 can switch S1 and S2.
(1)
Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
TZA3019
handbook, halfpage
GND 56 k
handbook, halfpage
GND
VCC LOS1, LOS2 5 k GND1A, GND2A ILOS VEE 5.6 k
TZA3019
5 k
LOS1, LOS2 GND1A, GND2A ILOS VEE
TZA3019
MGS561
MGS562
a. Negative supply and negative logic.
handbook, halfpage
b. Negative supply and positive logic.
VCC LOS1, LOS2 5 k GND1A, GND2A ILOS GND
MGS563
TZA3019
56 k
VCC - VEE < 7 V.
c. Positive supply and positive logic. Fig.11 Loss of signal outputs, pins LOS1 and LOS2.
Supply current For the supply currents IEE1B and IEE2B, see Fig.12. Using a positive supply voltage Although the TZA3019 has been designed to use a single -3.3 V supply voltage (see Fig.13), a +3.3 V supply (see Fig.14) can also be used. However, care should be taken with respect to RF transmission lines. The on-chip signals refer to the various ground pins as being positive supply pins in a +3.3 V application. The external transmission lines will most likely be referred to the pins VEE1A, VEE2A, VEE1B and VEE2B, being the system ground. The RF signals will change from one reference plane to another when interfacing the RF inputs and outputs. A positive supply application is very vulnerable to interference with respect to this point. For a successful +3.3 V application, special care should be taken when designing the PCB layout in order to reduce the influence of interference and to keep the positive supply voltage as clean as possible.
60
58
(1)
I EE1B, 50 I EE2B (mA) 40 30 20
17
10 5 0 0 0.2 0.8 0.5 Vo(se)(p-p) (V) 1
MGS566
(1) IEE1B and IEE2B at 25 C.
Fig.12 Supply current as a function of output voltage
2000 Apr 10
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Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VEE Vn negative supply voltage DC voltage pins IN1, IN1Q, IN2, IN2Q, LOSTH1, LOSTH2, LEVEL1, LEVEL2, VEE - 0.5 Vref, TEST, OUT2Q, OUT2, OUT1Q, OUT1, VEEP, GND1A, GND2A, GND1B and GND2B pins LOS1, LOS2, INV1, INV2, S1 and S2 In DC current pins IN1, IN1Q, IN2 and IN2Q pins LOSTH1, LOSTH2, LEVEL1 and LEVEL2 pins Vref, TEST, LOS1 and LOS2 pins OUT1, OUT1Q, OUT2 and OUT2Q pins INV1, INV2, S1 and S2 Ptot Tstg Tj Tamb total power dissipation storage temperature junction temperature ambient temperature -20 0 -1 -30 0 - -65 - -40 +20 14 +1 +30 20 1.2 +150 150 +85 VEE - 0.5 0.5 PARAMETER MIN. -5.5
TZA3019
MAX. +0.5 V V
UNIT
VEE + 7
V mA A mA mA A W C C C
THERMAL CHARACTERISTICS SYMBOL Rth(j-s) Rth(j-a) Rth(s-a) Rth(s-a)(req) PARAMETER thermal resistance from junction to solder point (exposed die pad); note 1 thermal resistance from junction to ambient; note 1 thermal resistance from solder point to ambient (exposed die pad); note 1 required thermal resistance from solder point to ambient 1s2p multi-layer test board 1s2p multi-layer test board LOS circuits switched on Vo = 200 mV (p-p) single-ended; both output circuits Vo = 800 mV (p-p) single-ended; both output circuits Note 1. JEDEC standard. 60 30 K/W K/W CONDITIONS VALUE 15 33 18 UNIT K/W K/W K/W
2000 Apr 10
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Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
TZA3019
CHARACTERISTICS Typical values at Tamb = 25 C and VEE = -3.3 V; minimum and maximum values are valid over the entire ambient temperature range and supply voltage range; all voltages referenced to ground; unless otherwise specified; note 1. SYMBOL Supply SUPPLY PINS VEE1A, VEE1B, VEE2A AND VEE2B VEE IEE1A, IEE2A IEE1B, IEE2B negative supply voltage negative supply current negative supply current LOS circuit power-down LOS circuit switched on amplifier power-down Vo = 200 mV (p-p) single-ended; one output circuit Vo = 800 mV (p-p) single-ended; one output circuit Ptot total power dissipation power-down both LOS circuits switched on Vo = 200 mV (p-p) single-ended; both output circuits Vo = 800 mV (p-p) single-ended; both output circuits TC temperature coefficient 220 380 555 mW -3.13 14 24 2 11 -3.3 24 40 6 17 -3.47 34 56 10 24 V mA mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
47
60
77
mA
100
200
300
mW
450
660
925
mW
LOS circuit switched on; IEE1A; 30 IEE2A Vo = 800 mV (p-p) single-ended; IEE1A; IEE2A 15 -40 -40
50 30 - +25
80 50 +125 +85
A/C A/C C C
Tj Tamb
junction temperature ambient temperature
Inputs multiplexer and loss of signal detector PECL OR CML INPUT PINS IN1, IN1Q, IN2 AND IN2Q Vi(p-p) Vi(bias) VI Ri Ci input voltage swing (peak-to-peak value) DC input bias voltage DC and AC input window voltage input resistance input capacitance note 3 single-ended single-ended; note 3 single-ended; note 2 50 -0.28 -1.0 35 0.6 - -0.33 - 50 0.8 500 -0.4 +0.3 70 1.2 mV V V pF
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Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
SYMBOL Postamplifier AMPLIFIERS A1A, A1B, A2A AND A2B Gv small signal voltage gain Vo = 200 mV (p-p) single-ended; note 4 Vo = 800 mV (p-p) single-ended; note 4 fD f-3dB(l) f-3dB(h) tPD tPD J ct Vo(se)(p-p) TC tr tf Ro Co Vi Ri signal path data rate low -3 dB cut-off frequency DC compensation high -3 dB cut-off frequency propagation delay propagation delay difference total jitter crosstalk note 3 at the same signal levels; note 3 20 bits of the 28.5kbits pattern; notes 3 and 6 crosstalk of IC only 50 load notes 5 and 9 note 3 10 22 - 2 - 150 - - 90 15 29 2500 5 2.0 200 0 8 110 - 0 80 80 100 0.8 - 350 19 34 - 10 - 250 5 - - 800 -1 - - 130 1.2 PARAMETER CONDITIONS MIN. TYP.
TZA3019
MAX.
UNIT
dB dB Mbits/s kHz GHz ps ps ps dB
PECL OR CML OUTPUT PINS OUT1, OUT1Q, OUT2 AND OUT2Q single-ended output voltage (peak-to-peak value) temperature coefficient output level rise time fall time output resistance output capacitance 20% to 80%; note 5 80% to 20%; note 5 single-ended single-ended; note 3 200 -1 - - 70 0.6 mV mV/K ps ps pF
LEVEL CONTROL INPUT PINS LEVEL1 AND LEVEL2 input voltage input resistance measured to GND1A or GND2A Vref 150 0 600 V k
Multiplexer and inverter switch PECL OR CML INPUT PINS IN1, IN1Q, IN2 AND IN2Q OS(red) input offset reduction Vo = 200 mV (p-p) single-ended; note 7 Vo = 800 mV (p-p) single-ended; note 7 Vio(cor) input offset voltage correction range peak-to-peak value single-ended Vo = 800 mV (p-p) single-ended; note 3 note 3 4 10 -10 - - 9 14 - 75 5 13 20 +10 170 12 dB dB mV V dB
Vn(i)(eq)(rms) equivalent input noise voltage (RMS value) Fn noise factor
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Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
SYMBOL SWITCH CIRCUIT ta td VIL VIH Ri Ii assert time de-assert time multiplexer and inverter multiplexer and inverter 70 55 100 80 - - - 180 - 200 160 PARAMETER CONDITIONS MIN. TYP.
TZA3019
MAX.
UNIT
ns ns
TTL INPUT PINS S1, S2, INV1 AND INV2 LOW-level input voltage HIGH-level input voltage input resistance input current positive logic negative logic negative logic positive logic measured to VEE1A or VEE2A 2.0 -1.3 -0.3 100 -10 VEE + 7.3 V -2.5 +0.3 +0.8 400 +10 V V V k A VEE - 0.3 -
Received Signal Strength Indicator and Loss Of Signal detector RSSI AND LOS CIRCUIT Vi(se)(p-p) DR SLOS single-ended input voltage swing (peak-to-peak value) dynamic range LOS sensitivity 50 MHz, square; note 8 620 MHz, square; note 8 1.2 GHz, square; note 8 100 MB/s PRBS note 8 (231 - 1); 0.4 57 11 10.7 10 11.2 10.9 10.7 -2 see Fig.10 notes 3 and 7 peak-to-peak value single-ended - 25 -5 0.5 1.5 - 60 12.5 11.9 11.1 12.7 12.4 11.9 0 0.5 35 - 1 2 400 63 14 13 12.2 14.2 13.9 13 -2 1 45 +5 2 2.5 mV dB mV/dB mV/dB mV/dB mV/dB mV/dB mV/dB V/dbK dB dB mV MHz GHz
1.2 GB/s PRBS (231 - 1); note 8 100 GB/s PRBS (231 - 1); note 8 TCsens LE OS(red) Vio(cor) f-3dB(l) f-3dB(h) LOS CIRCUIT hysLOS ta td Vi Ri LOS hysteresis assert time de-assert time input signal waveform dependency note 3 note 3 temperature coefficient sensitivity linearity error input offset reduction input offset voltage correction range low -3 dB cut-off frequency high -3 dB cut-off frequency note 8
2.0 - - VEE
3.0 - - - 350
4.0 5 5
dB S S V k
INPUT PINS LOSTH1 AND LOSTH2 input voltage input resistance measured to VEE1A or VEE2A 0 600 150
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Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
SYMBOL PARAMETER CONDITIONS MIN. - - 5 TYP.
TZA3019
MAX.
UNIT
OUTPUT PINS LOS1 AND LOS2 Vo Io(sink) Ro output voltage output sink current output resistance internal output series resistance VEE - 3.5 3.5 1 6.5 V mA k
OUTPUT PINS RSSI1 AND RSSI2 Vo Io output voltage output current -1 -1 - - 0 +1 V mA
Band gap reference circuit OUTPUT PIN VREF Vref Cext Io(sink) Notes 1. It is assumed that both CML inputs carry a complementary signal with the specified peak-to-peak value (true differential excitation). 2. Minimum signal with limiting output. 3. Guaranteed by design. Vo 4. GV = ----Vi 5. Based on -3dB cut-off frequency. 6. Vi = 100 mV (p-p) single-ended and Vo = 200 mV (p-p) single-ended. 7. Input offset reduction = G AC ---------G DC reference voltage allowed external capacitance output sink current -1.45 - - -1.6 - - -1.8 10 500 V pF A
8. Sensitivity depends on the waveform and is therefore a function of -3 dB cut-off frequency see equation (1). 9. Low limit can go as low as DC if input signal overrides input offset voltage correction range. APPLICATION INFORMATION RF input and output connections Striplines, or microstrips, with an odd mode characteristic impedance of Zo = 50 must be used for the differential RF connections on the PCB. This applies to both the signal inputs and the signal outputs. The two lines in each pair should have the same length. Grounding and power supply decoupling The ground connection on the PCB needs to be a large copper filled area connected to a common ground plane with an inductance as low as possible. All VEE pins (one at each corner and the exposed die pad) need to be connected to a common supply plane with an inductance as low as possible. This plane should be decoupled to ground. To avoid high frequency resonance, multiple bypass capacitors should not be mounted at the same location. To minimize low frequency switching noise in the vicinity of the TZA3019, the power supply line should be filtered once using a beaded capacitor circuit with a low cut-off frequency (see Figs 13 and 14). The VEE connection on the PCB also needs to be a large copper area to improve heat transfer to the PCB and thus support IC cooling.
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Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
TZA3019
handbook, full pagewidth
Boundary of 200 mm2 area GND GND VEE signal/VEEP
To central VEE decoupling 0603
VEE1A 32 INV1 INV2 LOS1 LOS2 VEE1B 25 S1 S2
0
1
2
3
4
5 mm
To central VEE decoupling 0603
31
30
29
28
27
26
0603
0603
24
1 2 3 4 5 6 7
GND1A IN1 IN1Q GND1A GND2A IN2 IN2Q GND2A
GND1B OUT1 OUT1Q GND1B GND2B OUT2 OUT2Q GND2B
23 22 21 20 19 18 17
0603
0603
0603
To central VEE decoupling
0603
0603
To central VEE decoupling
0603
0603
0603
0603
0603
0603
0603
HTQFP
MGS567
In order to enable heat flow out of the package, the following measures have to be taken: (1) Solder the 3 x 3 mm2 die pad to a plane with maximum size. (2) Add a plane with minimum 200 mm2 in an inner layer, surrounded by ground layers. (3) Use maximum amount of vias to connect two planes. (4) Use minimum of openings in heat transport area between hot plane and ground planes.
Fig.13 PCB layout for negative supply voltage.
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0603
8 9
VEE2A
0603
10 LOSTH1
11 LOSTH2
12 LEVEL1
13 LEVEL2
14 Vref
15 TEST
16 VEE2B
0603
Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
TZA3019
handbook, full pagewidth
0
1
2
3
4
5 mm
To central VEE decoupling 0603
To central VEE decoupling 0603
0603
0603
GND1A IN1 IN1Q GND1A GND2A IN2 IN2Q GND2A
GND1B OUT1 OUT1Q GND1B GND2B OUT2 OUT2Q GND2B
0603
0603 0603
0603
0603
To central VEE decoupling
0603
0603
To central VEE decoupling
0603
0603
0603
0603
0603
0603
0603
HTQFP
MGS568
In order to enable heat flow out of the package, the following measures have to be taken: (1) Solder the 3 x 3 mm2 die pad to a plane with maximum size. (2) Add a plane with minimum 200 mm2 in an inner layer, surrounded by ground layers. (3) Use maximum amount of vias to connect two planes. (4) Use minimum of openings in heat transport area between hot plane and ground planes.
Fig.14 PCB layout for positive supply voltage.
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0603
GND GND VEE signal/VEEP
24 23 22 21 20 19 18 17
Boundary of 200 mm2 area
LOS1
INV1
INV2
VEE1B 25
VEE1A 32
LOS2
S1
S2
31
30
29
28
27
26
1 2 3 4 5 6 7 8 16 VEE2B 9
VEE2A
10 LOSTH1
11 LOSTH2
12 LEVEL1
13 LEVEL2
14 Vref
15 TEST
Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
BONDING PAD LOCATIONS COORDINATES(1) SYMBOL GND1A IN1 IN1Q GND1A n.c. n.c. GND2A IN2 IN2Q GND2A VEE2A LOSTH1 LOSTH2 n.c. LEVEL1 LEVEL2 VREF n.c. TEST VEE2B GND2B OUT2Q 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PAD x -928 -928 -928 -928 -928 -928 -928 -928 -928 -928 -707 -550 -393 -236 -79 +79 +236 +393 +550 +707 +928 +928 +710 +553 +396 +239 +81 -81 -239 -396 -553 -710 -928 -928 -928 -928 -928 -928 -928 -928 -928 -928 -710 -553 y OUT2 GND2B n.c. n.c. GND1B OUT1Q OUT1 GND1B VEE1B RSSI2 LOS2 RSSI1 LOS1 INV2 INV1 S2 S1 VEE1A Note 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 +928 +928 +928 +928 +928 +928 +928 +928 +707 +550 +393 +236 +79 -79 -236 -393 -550 -707 SYMBOL PAD x
TZA3019
COORDINATES(1) y -396 -239 -81 +81 +239 +396 +553 +710 +928 +928 +928 +928 +928 +928 +928 +928 +928 +928
1. All x and y coordinates represent the position of the centre of the pad in m with respect to the centre of the die (see Fig.15)
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Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
TZA3019
VEE1A
RSSI1
40 39 38 37 36 35 34 33 32 31 GND1A IN1 IN1Q GND1A n.c. n.c. GND2A IN2 IN2Q GND2A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 x 0 0 y 30 29 28 27 26 25 24 23 GND1B OUT1 OUT1Q GND1B n.c. n.c. GND2B OUT2 OUT2Q GND2B
TZA3019U
RSSI2 TEST
LOS1
LOS2
handbook, full pagewidth
LOSTH1
LOSTH2
LEVEL2
n.c.
LEVEL1
VEE2B
VEE2A
n.c.
Vref
VEE1B 22 21
INV1
INV2
S1
S2
MGT030
Fig.15 Bonding pad locations TZA3019U.
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Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
PACKAGE OUTLINE HTQFP32: plastic, heatsink thin quad flat package; 32 leads; body 5 x 5 x 1.0 mm
TZA3019
SOT547-2
c y heathsink side X Dh 24 17 A ZE
25
16
e Eh wM bp Lp 32 pin 1 index 9 detail X 1 wM 8 ZD vM A L E HE A A2 A1 (A 3)
bp e D HD
B vM B
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.2 A1 0.15 0.05 A2 1.05 0.95 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D(1) 5.1 4.9 Dh 3.1 2.7 E(1) 5.1 4.9 Eh 3.1 2.7 e 0.5 HD 7.1 6.9 HE 7.1 6.9 L 1.0 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 ZD(1) ZE(1) 0.89 0.61 0.89 0.61 7 0
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT547-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 99-06-15
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Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
HBCC32: plastic, heatsink bottom chip carrier; 32 terminals; body 5 x 5 x 0.65 mm
TZA3019
SOT560-1
D
xB b1 wM wM
ball A1 index area
b
E
b3 wM b2 detail X wM
xC B e C e1 vA
A y
e2
E1 e4
1 32 D1 e3 X A2 A 0 2.5 scale DIMENSIONS (mm are the original dimensions) UNIT mm A max. 0.80 A1 0.10 0.05 A2 0.70 0.60 b 0.35 0.20 b1 0.50 0.30 b2 0.50 0.35 b3 0.50 0.35 D 5.1 4.9 D1 3.2 3.0 E 5.1 4.9 E1 3.2 3.0 e 0.5 e1 4.2 e2 4.2 e3 4.15 e4 4.15 v 0.2 w 0.15 x 0.15 y 0.05 5 mm A1
OUTLINE VERSION SOT560-1
REFERENCES IEC JEDEC MO-217 EIAJ
EUROPEAN PROJECTION
ISSUE DATE 99-09-10 00-02-01
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Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
TZA3019
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable suitable suitable suitable suitable suitable
TZA3019
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
DATA SHEET STATUS DATA SHEET STATUS Objective specification PRODUCT STATUS Development DEFINITIONS (1)
TZA3019
This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Preliminary specification
Qualification
Product specification
Production
Note 1. Please consult the most recently issued data sheet before initiating or completing a design. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
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Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
NOTES
TZA3019
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Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
NOTES
TZA3019
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Philips Semiconductors
Preliminary specification
2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch
NOTES
TZA3019
2000 Apr 10
31
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 69
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403510/50/01/pp32
Date of release: 2000
Apr 10
Document order number:
9397 750 06019

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